1. Field of the Invention
The present invention relates to a method of manufacturing a NAND flash memory device and, more particularly, to a method of manufacturing a NAND flash memory device capable of reducing the aspect ratio upon a metal contact process.
2. Discussion of Related Art
Information stored at the cells of a non-volatile memory device such as a flash memory device is not erased even when the power is off. For this reason, the flash memory device has been widely used in memory cards, etc. The flash memory device may be classified into two types. One of them is a NAND type flash memory device and the other is an OR type flash memory device.
The NAND flash memory device largely includes a cell region and a peripheral circuit region. The cell region consists of a plurality of strings, wherein a source select transistor, a plurality of memory cells and a drain select transistor are serially connected to each string. A source region of the source select transistor is connected to a common source line and a drain region of the drain select transistor is connected to a bit line. The peripheral circuit region consists of peri-transistors such as PMOS transistors, NMOS transistors, etc.
Meanwhile, a cell region of the NOR flash memory device includes a plurality of memory cells, bit lines and common source lines. Only a single memory cell is intervened between the bit lines and the common source lines.
Therefore, the NAND flash memory device has a higher integration level than the NOR flash memory device but requires a high cell current. At this time, the cell current means a current flowing into the bit lines and the common source lines while information stored at the memory cells is being read. Accordingly, more effort to increase the cell current in the NAND flash memory device is required than in.the NOR flash memory device. The reason is that the larger the cell current, the faster the access time of the flash memory device. As a result, in order to improve the operating speed of the NAND flash memory device, it is required to reduce the electrical resistance of the bit lines and/or the common source lines.
FIG. 1A is a cross-sectional view of a NAND flash memory device for explaining a conventional method of manufacturing the device, and FIG. 1B is a cross-sectional view of the NAND flash memory device that is taken along a region where a common source line will be formed in order to explain the conventional method of manufacturing the NAND flash memory device.
Referring to FIGS. 1A and 1B a plurality of isolation films 12 are formed in parallel to each other in given regions of a semiconductor substrate 11 to define an active region. The isolation films 12 are formed by means of a local oxidation of silicon (LOCOS) process or a trench isolation process. The trench isolation process has recently been widely used for a high integration of the device. The NAND flash memory device can be largely classified into a cell region and a peripheral circuit region. The cell region includes a plurality of strings, wherein a source select transistor SST, a plurality of memory cells MC1, . . . , MCn and a drain select transistor DST are serially connected to each string. A peri-transistor PT such as a PMOS transistor, a NMOS transistor, etc. is formed in the peripheral circuit region. Thereafter, a metal contact process for electrically connecting them is performed, which will be described later.
An etch-stop film 14 is formed on the entire structure. A first interlayer insulating film 15 is then formed on the resulting entire structure on which the etch-stop film 14 is formed. The surface of the first interlayer insulating film 15 is polished by means of a chemical mechanical polishing (CMP) process. The first interlayer insulating film 15 and the etch-stop film 14 are then etched by means of an etch process using a mask for the common source line, thus forming a common source line contact hole through which a cell source region 13S and the isolation films 12 are exposed. Next, a doped polysilicon layer is formed so that the common source line contact hole is filled. The doped polysilicon layer is then blanket-etched so that the first interlayer insulating film 15 is exposed, thereby forming a common source line CSL. This series of the process is referred to as so called a cell source poly plug process.
A second interlayer insulating film 18 is formed on the first interlayer insulating film 15 including the common source line CSL. The second interlayer insulating film 18, the first interlayer insulating film 15 and the etch-stop film 14 are then etched by means of an etch process using a mask for a drain contact, thus forming cell drain contact holes through which each cell drain region 13D is exposed. After forming a doped polysilicon layer so that the cell drain contact holes are buried, the doped polysilicon layer is blanket-etched so that the second interlayer insulating film 18 is exposed, thus forming cell drain contact plugs DCP. This series of the process is referred to as so called a cell drain poly plug process.
A trench nitride film 19 and a trench oxide film 20 are sequentially formed on the second interlayer insulating film 18 including the cell drain contact plugs (DCP). Next, damascene patterns are formed by a damascene process. After depositing a metal so that the damascene patterns are buried, a blanket etch process is implemented to form a metal wire 22S connected to the common source line CSL, a bit line 22D connected to the drain contact plug DCP, a metal wire 22G connected to a gate of the peri-transistor PT, and a metal wire 22P connected to a source/drain junction 13P of the peri-transistor PT.
As described above, according to the prior art, the thickness of the common source line CSL is decided by the first interlayer insulating film 15. In other words, the thicker the thickness of the first interlayer insulating film 15, the smaller the electrical resistance of the common source line CSL. Considering the electrical resistance of the common source line CSL, therefore, there is a limit in reducing the thickness of the first interlayer insulating film 15. Due to this, as this causes the aspect ratio to increase in a subsequent metal contact process, in particular the cell drain contact process, there is no choice but to first form the cell drain contact plug DCP. In case where the aspect ratio is severe, there is a difficulty in process that there is no choice but to perform a contact process for forming the metal wire 22G connected to the gate of the peri-transistor PT and the metal wire 22P connected to the source/drain junction 13P of the peri-transistor PT as an additional mask process.
Thus, in order to implement a high-performance NAND flash memory device, it is necessary to minimize the resistance of the common source line while preventing an increase in the aspect ratio of the contact hole for connecting the bit line 22D to the cell drain region 13D.
The present invention is contrived to solve the aforementioned problems. The present invention is directed to provide a method of manufacturing a NAND flash memory device capable of reducing the aspect ratio of a drain contact hole while reducing the resistance of a common source line.
One aspect of the present invention is to provide a method of manufacturing a NAND flash memory device, comprising the steps of: providing a semiconductor substrate in which a plurality of isolation films are formed in parallel to each other, a source select transistor having a cell source region, a plurality of memory cells having a cell impurity region and a drain select transistor having a cell drain region are serially connected and formed in each of a plurality of strings in a cell region, and a peri-transistor having a source/drain junction is formed in a peripheral circuit region; forming a first interlayer insulating film on the resulting semiconductor substrate; etching a portion of the first interlayer insulating film to expose the cell source regions and the isolation films between the regions, and then etching the exposed portions of the isolation films to form a common source line contact hole through which the semiconductor substrate is exposed; performing an ion implantation process to form an ion implantation region on the exposed semiconductor substrate at the bottom of the common source line contact hole; and burying a conductive material within the common source line contact hole in which the ion implantation region is formed, thus forming a common source line.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, before the step of forming the first interlayer insulating film, further comprising the step of forming an etch-stop film having a higher etch selective ratio than that of the first interlayer insulating film on the resulting semiconductor substrate.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, the step of forming the common source line contact hole comprises the steps of: etching a portion of the first interlayer insulating film to expose the etch-stop film; and etching the exposed etch-stop film to expose the cell source regions and the isolation films between the regions and then etching the exposed isolation films to expose the semiconductor substrate.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, the common source line contact hole includes, at its bottom, a continuous conductive line consisting of the cell source regions and the ion implantation regions formed between the cell source regions.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, the impurity ion implantation process is performed at a dose of 1E12 to 1E14 atom/cm2 with an implantation energy of 15 keV to 25 KeV, using arsenic or phosphorous as an impurity ion.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, the impurity ion implantation process is performed simultaneously with tilt implantation.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, at the time of the tilt implantation, a wafer is rotated.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, the step of forming the common source line comprises the steps of: depositing a doped polysilicon as the conductive material on the first interlayer insulating film so that the common source line contact hole, in which the ion implantation region is formed, is buried; and etching the deposited doped polysilicon layer until the first interlayer insulating film is removed to a given thickness by means of a blanket etch process.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, the blanket etch process is performed until the top surface of the source select transistor is exposed.
In the aforementioned of a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, after the step of forming the common source line, further comprising the steps of; forming a second interlayer insulating film on the first interlayer insulating film including the common source line; forming a trench etch-stop film and a trench insulating film on the second interlayer insulating film sequentially; forming a plurality of damascene patterns simultaneously by means of a damascene process; and burying a metal within the damascene patterns to form a metal wire connected to the common source line, a bit line connected to the cell drain region, a metal wire connected to a gate of the peri-transistor, and a metal wire connected to the source/drain junction of the peri-transistor, separately.